EVE Wraps up 45th DAC and SNUG

EVE Presents ZEMI-3 and Papers at DAC

"ZEMI-3 is a key component of our hardware-debugging offering," said EVE CEO and President Dr. Luc Burgun at the 45th Design Automation Conference (DAC) in June. With ZEMI-3, it is easy to develop bus-functional models (BFMs), because of the product's embedded behavioral compiler. In the emulated designs-under-test (DUTs) and the testbench, clocks are synchronized automatically and only when needed. In addition, the product automatically streams data when possible, making sure the data is moved to its destination before it's needed.

More Products

In addition to introducing the ZEMI-3 at DAC in June, EVE also launched other product enhancements. In its extensive library of the most common standard protocols, the company demonstrated two new transactors: an AXI Master/Slave transactor and a PCIe Gen 2.0 16x transactor.

Both connect easily to the design, reducing testbench setup time by eliminating the need for hardware speed bridges or synthesizable testbenches. The two transactors offer a high-level application programming interface (API), enabling the designer to quickly create application-oriented test sequences.

The AXI and PCIe Gen 2.0 transactors start at $15,000, and you can order them now.

Special DAC Sessions

EVE also presented four special sessions at DAC to help your design engineers better understand how to get the most out of their simulations.

• Easy FPGA Prototyping with Xilinx Virtex-5 showed the audience members how to combine the fastest and largest FPGAs to date with full RTL visibility and allowed them to discover what an amazing prototyping platform they can build.
• HW/SW Co-Verification Methodology explained how to use multiple concurrent levels of abstraction to verify hardware and software simultaneously. The methodology uses a platform that delivers billions of cycles per simulation and that is capable of booting operating systems, debugging device drivers and even full applications.
• ESL and Transaction-Level explained how to mix a transaction-level testbench or ESL environment with emulation.
• ARM Emulation revealed the tricks to connecting your favorite software debugger to an emulator. The session also explained whether it's best for you to use a CCM model, RTL or Logic Tile and showed how you should figure in other key IP such as AMBA or AXI buses.

ZeBu Gets Personal at DATE

During Design Automation & Test in Europe (DATE) at ICM in Munich, Germany, March 11-13, EVE demonstrated its ZeBu-Personal for system-on-chip (SoC) hardware verification and software development.

The demonstration showed how ZeBu-Personal speeds up many aspects of the verification cycle while improving product quality and eliminating costly re-spins – letting you move your software development ahead of silicon. Using the same hardware, models and engineering across the entire design cycle also makes it cost effective for any design team.

ZeBu-Personal uses EVE's patented reconfigurable test bench (RTB) to deliver the fastest co-emulation of any software test bench. The product can reach 60 MHz during co-emulation at the transaction level and handles up to 5 million gates.

By using the RTB, your designers can perform memory testing and register read/write and continuous internal state capture. The RTB also generates waveforms for Novas' waveform format FSDB, the standard Verilog waveform format VCD and Synopsys' waveform format VPD. ZeBu-Personal offers designers an instant snapshot and logic analysis with triggers and high-speed trace memory, as well as state save and restore within the emulator or in on-emulation with hardware description language simulators.

To find out more about ZeBu-Personal, go to EVE's Web site.

EVE Gets SNUG with Synopsys in Santa Clara

In April, EVE demonstrated its ZeBu system-on-chip (SoC) hardware and embedded software co-verification solution at the Synopsys Users Group (SNUG) Interoperability Fair.

Held at the Santa Clara Convention Center, the fair was an opportunity for EVE to show how ZeBu accelerates software development ahead of silicon and uses the same hardware, models and engineering across the entire design cycle. These streamlining features make ZeBu a cost-effective tool for any design team. The fair showed how Synopsys and others are helping to solve semiconductor design challenges through interoperability programs and strategic alliances.