Boost Your Simulation Performance

Under time-to-market pressures, systems engineers must turn to virtualization to explore the micro-architectures of system-on-chip (SoC) electronic control units as well as other systems when they develop and verify software. They look to these virtual system prototypes (VSPs) to validate simulation speed and accuracy under different usage loads. Often, the modeling is in SystemC, a modeling language based on C++ that has a synthesizable subset.

Standards fall short

Although the newest SystemC standards (OSCI TLM 2.0, OCP IP TL2, etc.) are important steps forward, they don't offer the complete answer. Instead, the standards focus on the bus interfaces for peripheral devices connected to a virtual simulation system, and some recent proposals are trying to extend them into the runtime configuration of the hardware simulation models. The drawback of the standards is that they don't assure fast simulation speeds when applied to a processor-heavy system. This limitation is particularly applicable to the programmer's view and the programmer's timing view. A second drawback is that these standards don't support efficient modeling techniques when they're applied to a simulation IP block.

Inefficient modeling of processor behavior decreases simulation to kilo instructions per second (KIPS), far below the million instructions per second (MIPS) needed by software designers who must create their applications on virtual platforms.

White paper explains how

To address this problem, VaST is offering a new white paper, "SystemC: Key Modeling Concepts Besides TLM to Boost Your Simulation Performance," which explains an efficient virtual-hardware modeling methodology that minimizes events to keep speeds in the MIPS range and yet maintain accurate simulation cycle boundaries. The paper explains how to use a "watchdog timer" to show elementary SC_METHOD concepts and deliver the promised MIPS simulation speeds for a decent number of complex devices. The paper's authors used the modeling methodology described in the white paper in a SystemC subsystem containing an interrupt controller, a UART and a timer model.

Besides explaining how to keep simulation speeds high, the white paper also points out some of the current SystemC SC_METHOD weaknesses.

Read the complete white paper at http://www.vastsystems.com/documents/SystemCKeyModelingConcepts.pdf.